Mechanical strains within a semiconductor device substrate can modulate device performance by, for example, increasing the mobility of the carriers in the semiconductor device. That is, strains within a semiconductor device are known to enhance semiconductor device characteristics. Thus, to improve the characteristics of a semiconductor device, tensile and/or compressive strains are created in the channel of the n-type devices (e.g., NFETs) and/or p-type devices (e.g., PFETs), respectively. However, the same strain component, for example tensile strain or compressive strain, improves the device characteristics of one type of device (i.e., n-type device or p-type device) while discriminatively affecting the characteristics of the other type device.
Accordingly, in order to maximize the performance of both NFETs and PFETs within integrated circuit (IC) devices, the strain components should be engineered and applied differently for NFETs and PFETs. That is, because the type of strain which is beneficial for the performance of an NFET is generally disadvantageous for the performance of the PFET. More particularly, when a device is in tension (in the direction of current flow in a planar device), the performance characteristics of the NFET are enhanced while the performance characteristics of the PFET are diminished.
To increase the strain levels in a device, a SiGe layer has been used in combination with a silicon layer. When epitaxially grown on silicon, an unrelaxed SiGe layer will have a lattice constant that conforms to that of the silicon substrate. Upon relaxation (through a high temperature process for example), the SiGe lattice constant approaches that of its intrinsic lattice constant which is larger than that of silicon. Accordingly, when a silicon layer is epitaxially grown on the SiGe, the silicon layer conforms to the larger lattice constant of the relaxed SiGe layer that results in a physical biaxial strain (e.g., expansion) to the silicon layer. This physical strain applied to the silicon layer is beneficial to the devices. While methods using SiGe provide improved device performance, additional and complex processing is required to form the gate structures, liners, spacers, etc. thus resulting in higher cost.
Alternatively, to selectively create tensile strain in an NFET and compressive strain in a PFET, distinctive processes and different combinations of materials can be used such as, for example, liners on gate sidewalls. The liners selectively induce the appropriate strain in the channels of the FET devices. While this provides tensile strain to the NFET device and compressive strain along the longitudinal direction of the PFET device, they still require additional materials and/or more complex processing, and thus, result in higher cost. For example, additional processing steps are needed to form the gate structures for both the NFET and PFET type devices.
Thus, it is desired to provide more cost-effective and simplified methods for creating tensile and compressive strains in the channels of the NFETs and PFETs, respectively. Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.